The present application relates generally to an improved data processing apparatus and method and more specifically to mechanisms for power management of microprocessors with “Pstates,” which represent an abstraction of frequencies and voltages.
Pstates are typically controlled by an operating system or hypervisor and are used to request a desired performance level for one microprocessor core or a set of microprocessor cores. In order to obtain optimum savings based on a Pstate request, hardware automatically switches not only the frequency of the core, but also the voltage, if possible, in order to save power. For cost reasons, many microprocessor cores on a chip share a single voltage plane and a single voltage controller. Further, a central power control entity (CPCE) decides which voltage to use. If the frequency and voltage is organized in one centralized table of the chip, the action of changing a Pstate requires interaction between the individual microprocessor cores and the CPGE. Such an approach does not scale well with the number of cores due to communication and processing overhead and that such an approach introduces unnecessary delays that result in suboptimal power savings.